Technology - Broadband Power Line 3 - OPERA, DS2 BPL and Co-Existence

Synopsis

This report provides a detailed overview of the 2006 OPERA BPL standard, survey of powerline architectures, attenuation and noise and of the 2007 OPERA Phase 2 project and its field trials. We discuss the DS2 chipsets, practical data rates which can be expected for access BPL systems and for in-home PLC systems and PLC market requirements developed by the Universal Powerline Association.

Table of Contents

• 1. Synopsis
  
• 2. DS2
  
• 3. The EU OPERA project
  
  • 3.1 Phase 2
    
  • 3.2 Access, rather than in-house
    
  • 3.3 The 2006 OPERA standard
    
    • 3.3.1 Head End, Repeaters and CPE
      
    • 3.3.2 PHY frame and symbol times
      
    • 3.3.3 Token passing
      
    • 3.3.4 Modulation and bits per carrier
      
    • 3.3.5 HURTO modulation
      
    • 3.3.6 Co-existence
      
    • 3.3.7 UPA coexistence standard V1.0
      
  • 3.4 OPERA field surveys
    
    • 3.4.1 LV Signal-to-Noise Ratio and theoretical data rates
      
    • 3.4.2 In-Home attenuation and noise
      
    • 3.4.3 MV signal to noise ratio and theoretical data rates
      
  • 3.5 OPERA Phase 2 field trials
    
  • 3.6 Large numbers of repeaters
    
• 4. Practical data rates
  
  • 4.1 OPERA
    
  • 4.2 HomePlug AV
    
• 5. Market requirements for access BPL and in-home PLC
  
• 6. Related reports
  

• Exhibit 1 – OPERA Phase 2 Field Trials